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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5097d 05h /
25 added sync FIFO unneback 5097d 19h /
24 added vl_dff_ce_set unneback 5099d 03h /
23 fixed port map error in async fifo 1r1w unneback 5099d 17h /
22 added binary counters unneback 5099d 22h /
21 reg -> wire in and or mux in logic unneback 5100d 19h /
20 naming convention vl_ unneback 5102d 05h /
19 naming convention vl_ unneback 5102d 05h /
18 naming convention vl_ unneback 5102d 06h /
17 unneback 5165d 19h /
16 converting utility for ROM unneback 5166d 06h /
15 added delay line unneback 5172d 03h /
14 reg -> wire for various signals unneback 5172d 08h /
13 cosmetic update unneback 5172d 09h /
12 added wishbone comliant modules unneback 5173d 05h /
11 async fifo simplex unneback 5173d 20h /
10 added dff_ce_clear unneback 5175d 19h /
9 added dff_ce_clear unneback 5175d 19h /
8 added dff_ce_clear unneback 5175d 19h /
7 mem update unneback 5175d 20h /

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