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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 5099d 18h /
27 added sync simplex FIFO unneback 5099d 18h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5099d 19h /
25 added sync FIFO unneback 5100d 09h /
24 added vl_dff_ce_set unneback 5101d 16h /
23 fixed port map error in async fifo 1r1w unneback 5102d 07h /
22 added binary counters unneback 5102d 12h /
21 reg -> wire in and or mux in logic unneback 5103d 08h /
20 naming convention vl_ unneback 5104d 19h /
19 naming convention vl_ unneback 5104d 19h /
18 naming convention vl_ unneback 5104d 19h /
17 unneback 5168d 09h /
16 converting utility for ROM unneback 5168d 20h /
15 added delay line unneback 5174d 16h /
14 reg -> wire for various signals unneback 5174d 22h /
13 cosmetic update unneback 5174d 23h /
12 added wishbone comliant modules unneback 5175d 19h /
11 async fifo simplex unneback 5176d 10h /
10 added dff_ce_clear unneback 5178d 09h /
9 added dff_ce_clear unneback 5178d 09h /

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