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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 5092d 07h /
28 added sync simplex FIFO unneback 5093d 08h /
27 added sync simplex FIFO unneback 5093d 08h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5093d 10h /
25 added sync FIFO unneback 5093d 23h /
24 added vl_dff_ce_set unneback 5095d 07h /
23 fixed port map error in async fifo 1r1w unneback 5095d 22h /
22 added binary counters unneback 5096d 03h /
21 reg -> wire in and or mux in logic unneback 5096d 23h /
20 naming convention vl_ unneback 5098d 10h /
19 naming convention vl_ unneback 5098d 10h /
18 naming convention vl_ unneback 5098d 10h /
17 unneback 5161d 23h /
16 converting utility for ROM unneback 5162d 11h /
15 added delay line unneback 5168d 07h /
14 reg -> wire for various signals unneback 5168d 12h /
13 cosmetic update unneback 5168d 14h /
12 added wishbone comliant modules unneback 5169d 10h /
11 async fifo simplex unneback 5170d 01h /
10 added dff_ce_clear unneback 5171d 23h /

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