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Rev Log message Author Age Path
31 sync FIFO updated unneback 5096d 01h /
30 updated counter for level1 and level2 function unneback 5096d 01h /
29 updated counter for level1 and level2 function unneback 5096d 01h /
28 added sync simplex FIFO unneback 5097d 03h /
27 added sync simplex FIFO unneback 5097d 03h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5097d 04h /
25 added sync FIFO unneback 5097d 18h /
24 added vl_dff_ce_set unneback 5099d 01h /
23 fixed port map error in async fifo 1r1w unneback 5099d 16h /
22 added binary counters unneback 5099d 21h /
21 reg -> wire in and or mux in logic unneback 5100d 17h /
20 naming convention vl_ unneback 5102d 04h /
19 naming convention vl_ unneback 5102d 04h /
18 naming convention vl_ unneback 5102d 04h /
17 unneback 5165d 18h /
16 converting utility for ROM unneback 5166d 05h /
15 added delay line unneback 5172d 01h /
14 reg -> wire for various signals unneback 5172d 07h /
13 cosmetic update unneback 5172d 08h /
12 added wishbone comliant modules unneback 5173d 04h /

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