URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 18

Rev	Log message	Author	Age	Path
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5490d 06h	/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5493d 05h	/
16	Added fizzim.pl	mikaeljf	5493d 06h	/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5494d 06h	/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5584d 08h	/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5584d 11h	/
12	Minor update of whishbone FSMs in TB	mikaeljf	5594d 12h	/
11	Initial version with support for DDR	mikaeljf	5594d 23h	/
10		unneback	5622d 07h	/
9	testbench	unneback	5622d 07h	/
8		unneback	5718d 04h	/
7		unneback	5718d 04h	/
6		unneback	5718d 04h	/
5	pass initial testing	unneback	5718d 04h	/
4		unneback	5719d 07h	/
3		unneback	5719d 10h	/
2	initial	unneback	5725d 08h	/
1	The project was created and the structure was created	root	5725d 08h	/