URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 19

Rev	Log message	Author	Age	Path
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5402d 15h	/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5403d 12h	/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5406d 11h	/
16	Added fizzim.pl	mikaeljf	5406d 12h	/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5407d 12h	/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5497d 14h	/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5497d 17h	/
12	Minor update of whishbone FSMs in TB	mikaeljf	5507d 18h	/
11	Initial version with support for DDR	mikaeljf	5508d 06h	/
10		unneback	5535d 14h	/
9	testbench	unneback	5535d 14h	/
8		unneback	5631d 10h	/
7		unneback	5631d 10h	/
6		unneback	5631d 10h	/
5	pass initial testing	unneback	5631d 11h	/
4		unneback	5632d 13h	/
3		unneback	5632d 16h	/
2	initial	unneback	5638d 14h	/
1	The project was created and the structure was created	root	5638d 14h	/