URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 29

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Rev	Log message	Author	Age	Path
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5483d 21h	/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5483d 23h	/
27		unneback	5487d 14h	/
26	compiles OK, not simulated	unneback	5489d 13h	/
25		unneback	5489d 16h	/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5490d 03h	/
23	Removed redundant code.	mikaeljf	5497d 20h	/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5499d 16h	/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5503d 19h	/
20	Minor update of sdc-file.	mikaeljf	5505d 20h	/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5512d 01h	/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5512d 22h	/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5515d 21h	/
16	Added fizzim.pl	mikaeljf	5515d 21h	/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5516d 21h	/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5607d 00h	/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5607d 03h	/
12	Minor update of whishbone FSMs in TB	mikaeljf	5617d 03h	/
11	Initial version with support for DDR	mikaeljf	5617d 15h	/
10		unneback	5644d 23h	/

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Subversion Repositories versatile_mem_ctrl

[/] - Rev 29

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