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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

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Rev Log message Author Age Path
32 Updated the testbench to match the new wishbone interface. mikaeljf 5377d 16h /
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5379d 10h /
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5379d 10h /
29 Adapted the test bench to the new wishbone interface. mikaeljf 5383d 10h /
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5383d 12h /
27 unneback 5387d 03h /
26 compiles OK, not simulated unneback 5389d 02h /
25 unneback 5389d 05h /
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5389d 16h /
23 Removed redundant code. mikaeljf 5397d 09h /
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5399d 05h /
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5403d 08h /
20 Minor update of sdc-file. mikaeljf 5405d 09h /
19 Added do-file for Modelsim waveform viewer. mikaeljf 5411d 14h /
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5412d 11h /
17 Modified rtl Makefile and tb_defines.v mikaeljf 5415d 10h /
16 Added fizzim.pl mikaeljf 5415d 10h /
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5416d 10h /
14 Added external feedback of DDR SDRAM clock. mikaeljf 5506d 13h /
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5506d 16h /

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