URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 39

Rev	Log message	Author	Age	Path
39	updated FIFO and SDR 16	unneback	5471d 01h	/
38	casex in rw state to save logic	unneback	5473d 09h	/
37		unneback	5473d 23h	/
36		unneback	5474d 00h	/
35	work for limited test case	unneback	5474d 07h	/
34	added	unneback	5474d 07h	/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5474d 10h	/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5477d 14h	/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5479d 07h	/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5479d 07h	/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5483d 07h	/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5483d 09h	/
27		unneback	5487d 00h	/
26	compiles OK, not simulated	unneback	5488d 23h	/
25		unneback	5489d 02h	/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5489d 13h	/
23	Removed redundant code.	mikaeljf	5497d 06h	/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5499d 02h	/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5503d 05h	/
20	Minor update of sdc-file.	mikaeljf	5505d 06h	/