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Rev Log message Author Age Path
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5346d 17h /
57 added support for early termination of burst access unneback 5347d 19h /
56 corrected fifo_rd_data in state w4d unneback 5349d 12h /
55 Fixed up sdr16 dqm output julius 5350d 07h /
54 dqm moved into FSM unneback 5351d 04h /
53 unneback 5351d 04h /
52 act exit for read updated unneback 5352d 06h /
51 act exit for read updated unneback 5352d 06h /
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5352d 08h /
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5352d 10h /
48 dq_oe fix unneback 5352d 10h /
47 support for registered outputs on ras, cas and we unneback 5352d 10h /
46 cosmetic updates unneback 5352d 11h /
45 added unneback 5352d 14h /
44 registered row comparison unneback 5354d 13h /
43 unneback 5354d 19h /
42 added pipeline stage for egress FIFO readot unneback 5355d 03h /
41 Added two alternate data capture functions. mikaeljf 5355d 10h /
40 updated fifo interfaces with re/rd and we/wr unneback 5355d 17h /
39 updated FIFO and SDR 16 unneback 5356d 05h /

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