URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 64

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Rev	Log message	Author	Age	Path
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5456d 03h	/
63	Fixed a couple of sdr_16 bugs to do with tracking of opened banks	julius	5456d 11h	/
62	Added note to sdr_16_defines.v asking if it's still used	julius	5456d 13h	/
61	Fixed blocking/nonblocking assign issue in sdr_16 fsm	julius	5460d 11h	/
60	Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation.	julius	5460d 11h	/
59	counter changed to shift register	unneback	5460d 13h	/
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5461d 14h	/
57	added support for early termination of burst access	unneback	5462d 16h	/
56	corrected fifo_rd_data in state w4d	unneback	5464d 09h	/
55	Fixed up sdr16 dqm output	julius	5465d 04h	/
54	dqm moved into FSM	unneback	5466d 01h	/
53		unneback	5466d 01h	/
52	act exit for read updated	unneback	5467d 03h	/
51	act exit for read updated	unneback	5467d 03h	/
50	Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily	julius	5467d 05h	/
49	Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project	julius	5467d 07h	/
48	dq_oe fix	unneback	5467d 07h	/
47	support for registered outputs on ras, cas and we	unneback	5467d 07h	/
46	cosmetic updates	unneback	5467d 08h	/
45	added	unneback	5467d 10h	/

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Subversion Repositories versatile_mem_ctrl

[/] - Rev 64

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