URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 71

Rev	Log message	Author	Age	Path
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5344d 09h	/
70		mikaeljf	5347d 15h	/
69		mikaeljf	5348d 12h	/
68	cleaqnup	unneback	5350d 00h	/
67	added FSM for wb if	unneback	5350d 00h	/
66		unneback	5350d 03h	/
65	added	unneback	5350d 03h	/
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5351d 02h	/
63	Fixed a couple of sdr_16 bugs to do with tracking of opened banks	julius	5351d 10h	/
62	Added note to sdr_16_defines.v asking if it's still used	julius	5351d 12h	/
61	Fixed blocking/nonblocking assign issue in sdr_16 fsm	julius	5355d 10h	/
60	Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation.	julius	5355d 10h	/
59	counter changed to shift register	unneback	5355d 12h	/
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5356d 13h	/
57	added support for early termination of burst access	unneback	5357d 15h	/
56	corrected fifo_rd_data in state w4d	unneback	5359d 08h	/
55	Fixed up sdr16 dqm output	julius	5360d 03h	/
54	dqm moved into FSM	unneback	5361d 00h	/
53		unneback	5361d 00h	/
52	act exit for read updated	unneback	5362d 02h	/