URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 77

Rev	Log message	Author	Age	Path
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5331d 10h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5336d 11h	/
75		mikaeljf	5336d 12h	/
74	Minor update of rtl Makefile.	mikaeljf	5340d 11h	/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5340d 12h	/
72	Restored lost revisions 69 and 70.	mikaeljf	5340d 13h	/
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5340d 14h	/
70		mikaeljf	5343d 20h	/
69		mikaeljf	5344d 17h	/
68	cleaqnup	unneback	5346d 05h	/
67	added FSM for wb if	unneback	5346d 05h	/
66		unneback	5346d 08h	/
65	added	unneback	5346d 08h	/
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5347d 07h	/
63	Fixed a couple of sdr_16 bugs to do with tracking of opened banks	julius	5347d 15h	/
62	Added note to sdr_16_defines.v asking if it's still used	julius	5347d 17h	/
61	Fixed blocking/nonblocking assign issue in sdr_16 fsm	julius	5351d 15h	/
60	Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation.	julius	5351d 15h	/
59	counter changed to shift register	unneback	5351d 17h	/
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5352d 18h	/