URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 83

Rev	Log message	Author	Age	Path
83		mikaeljf	5132d 04h	/
82		mikaeljf	5132d 08h	/
81		mikaeljf	5133d 05h	/
80		mikaeljf	5133d 06h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5170d 20h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5173d 03h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5181d 01h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5186d 02h	/
75		mikaeljf	5186d 03h	/
74	Minor update of rtl Makefile.	mikaeljf	5190d 02h	/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5190d 03h	/
72	Restored lost revisions 69 and 70.	mikaeljf	5190d 04h	/
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5190d 05h	/
70		mikaeljf	5193d 11h	/
69		mikaeljf	5194d 08h	/
68	cleaqnup	unneback	5195d 20h	/
67	added FSM for wb if	unneback	5195d 20h	/
66		unneback	5195d 23h	/
65	added	unneback	5195d 23h	/
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5196d 22h	/