URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 90

Rev	Log message	Author	Age	Path
90		unneback	5211d 16h	/
89		unneback	5211d 16h	/
88		unneback	5211d 16h	/
87		unneback	5211d 16h	/
86		mikaeljf	5264d 00h	/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5265d 00h	/
84		mikaeljf	5268d 23h	/
83		mikaeljf	5269d 18h	/
82		mikaeljf	5269d 22h	/
81		mikaeljf	5270d 19h	/
80		mikaeljf	5270d 20h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5308d 10h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5310d 17h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5318d 15h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5323d 16h	/
75		mikaeljf	5323d 17h	/
74	Minor update of rtl Makefile.	mikaeljf	5327d 16h	/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5327d 17h	/
72	Restored lost revisions 69 and 70.	mikaeljf	5327d 18h	/
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5327d 19h	/