URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 95

Rev	Log message	Author	Age	Path
95	new files	unneback	5205d 00h	/
94	new TB	unneback	5213d 07h	/
93		unneback	5224d 05h	/
92		unneback	5224d 05h	/
91		unneback	5224d 05h	/
90		unneback	5224d 05h	/
89		unneback	5224d 05h	/
88		unneback	5224d 05h	/
87		unneback	5224d 05h	/
86		mikaeljf	5276d 12h	/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5277d 12h	/
84		mikaeljf	5281d 11h	/
83		mikaeljf	5282d 06h	/
82		mikaeljf	5282d 11h	/
81		mikaeljf	5283d 07h	/
80		mikaeljf	5283d 08h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5320d 22h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5323d 05h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5331d 03h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5336d 04h	/