URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

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Rev	Log message	Author	Age	Path
64	Added old uploaded documents to new repository.	root	5738d 11h	/
63	Added old uploaded documents to new repository.	root	5738d 17h	/
62	New directory structure.	root	5738d 17h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7733d 14h	/
60	all WB outputs are registered, but just when we dont use cursors	markom	7733d 14h	/
59	Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.	rherveille	7765d 20h	/
58	Enabled Fifo Underrun test	rherveille	7765d 20h	/
57	1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. 2) Changed top level and pixel generator to reflect changes in the fifo. 3) Changed a bug in vga_fifo. 4) Changed pixel generator and wishbone master to reflect changes.	rherveille	7786d 15h	/
56	Removed 'or negedge arst' from sluint/luint sensitivity list	rherveille	7815d 12h	/
55	Initial release.	rherveille	7872d 12h	/
54	Added DVI tests	rherveille	7872d 13h	/
53	Fixed some Wishbone RevB.3 related bugs. Changed layout of the core. Blocks are located more logically now. Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.	rherveille	7872d 17h	/
52	Numerous updates and added checks	rherveille	7872d 17h	/
51	Forgot to change document revision number	rherveille	7920d 12h	/
50	Forgot to change document revision	rherveille	7920d 12h	/
49	Added WISHBONE revB.3 signals	rherveille	7920d 13h	/
48	WISHBONE revB.3 signals added	rherveille	7920d 13h	/
47	Added wb_b3_check Removed ud_cnt, ro_cnt	rherveille	7921d 10h	/
46	Added WISHBONE revB.3 sanity checks	rherveille	7921d 10h	/
45	Changed timing generator; made it smaller and easier.	rherveille	7921d 14h	/

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Subversion Repositories vga_lcd

[/] - Rev 64

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