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Rev Log message Author Age Path
25 C-include file.
Initial release		 rherveille 8393d 09h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8400d 12h /
23 Added Copyright/Licence header rherveille 8401d 07h /
22 VGA Core v2.0
Document revision 0.7		 rherveille 8421d 04h /
21 VGA Core v2.0
Document revision 0.7		 rherveille 8421d 04h /
20 Switched parameter order. rherveille 8430d 08h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8430d 10h /
18 Removed files. They are not used anymore. rherveille 8459d 07h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8459d 07h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8486d 13h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8522d 03h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8522d 22h /
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8523d 11h /
12 Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd);
adds color-lookup-table to the VGA core (i.e. on-chip CLUT).
Ram generation has been tested with Altera and Xilinx parts.		 rherveille 8532d 14h /
11 Major bug fixes in Wishbone Master and ColorProcessor blocks.
Core did not respond correctly to delayed ACK_I signals.

Added built-in Color Lookup Tables.		 rherveille 8532d 14h /
10 Design now uses Xilinx-BlockRAMs instead of selectRAM rherveille 8539d 06h /
9 no message rherveille 8539d 23h /
8 Revised core. Removed unused signals rherveille 8545d 07h /
7 revised counter.vhd rherveille 8549d 09h /
6 no message rherveille 8550d 09h /

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