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Rev Log message Author Age Path
29 Added wb_ack delay section to testbench rherveille 8335d 17h /
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8345d 19h /
27 Added 32bpp
Fixed some typos
Added bandwidth section		 rherveille 8345d 19h /
26 Added 32bpp tests rherveille 8345d 19h /
25 C-include file.
Initial release		 rherveille 8412d 13h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8419d 16h /
23 Added Copyright/Licence header rherveille 8420d 11h /
22 VGA Core v2.0
Document revision 0.7		 rherveille 8440d 08h /
21 VGA Core v2.0
Document revision 0.7		 rherveille 8440d 08h /
20 Switched parameter order. rherveille 8449d 13h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8449d 14h /
18 Removed files. They are not used anymore. rherveille 8478d 11h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8478d 11h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8505d 17h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8541d 07h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8542d 02h /
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8542d 15h /
12 Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd);
adds color-lookup-table to the VGA core (i.e. on-chip CLUT).
Ram generation has been tested with Altera and Xilinx parts.		 rherveille 8551d 18h /
11 Major bug fixes in Wishbone Master and ColorProcessor blocks.
Core did not respond correctly to delayed ACK_I signals.

Added built-in Color Lookup Tables.		 rherveille 8551d 18h /
10 Design now uses Xilinx-BlockRAMs instead of selectRAM rherveille 8558d 10h /

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