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Rev Log message Author Age Path
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7613d 21h /
58 Enabled Fifo Underrun test rherveille 7613d 21h /
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7634d 16h /
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7663d 13h /
55 Initial release. rherveille 7720d 13h /
54 Added DVI tests rherveille 7720d 13h /
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7720d 18h /
52 Numerous updates and added checks rherveille 7720d 18h /
51 Forgot to change document revision number rherveille 7768d 13h /
50 Forgot to change document revision rherveille 7768d 13h /
49 Added WISHBONE revB.3 signals rherveille 7768d 14h /
48 WISHBONE revB.3 signals added rherveille 7768d 14h /
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7769d 11h /
46 Added WISHBONE revB.3 sanity checks rherveille 7769d 11h /
45 Changed timing generator; made it smaller and easier. rherveille 7769d 15h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7769d 16h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7770d 06h /
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8102d 17h /
41 specs version 1.1 rherveille 8102d 17h /
40 no message rherveille 8102d 17h /

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