OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] - Rev 19

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
19 * driver/README updated oussamak 3374d 18h /
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3374d 20h /
17 Changed name of toplevel, to make tree consistent oussamak 3388d 22h /
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3438d 16h /
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3438d 16h /
14 RENAMED:
-- simulation folder		 aborga 3438d 18h /
13 RENAMED:
-- script		 aborga 3438d 18h /
12 Fixed http://opencores.org/bug,view,2524 fransschreuder 3513d 18h /
11 MODIFIED:
-- updated documentation		 aborga 3526d 15h /
10 Changed:
LOC => Package_pin		 fransschreuder 3536d 16h /
9 Added actual version information (Build date and svn revision) in BOARD_ID register fransschreuder 3565d 14h /
8 Changed:
* Added support for circular DMA (wrap around)
* Fixed Read / Write interrupts		 fransschreuder 3565d 20h /
7 Changed:
* Simplified address calculation to relax timing
* Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing
* Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk
* Added support for the High tech Global HTG710 board		 fransschreuder 3605d 16h /
6 Changed:
* fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable
* Fixed missing signals in sensitivity list		 fransschreuder 3611d 14h /
5 Changed:
* Added two registers to test interrupts vectors 2 and 3
* Added a register to read generic constants to show number of interrupts / number of descriptors
* fixed consistency of generic default values among different design units
* fixed route of pll_locked / register map record, to allow non-flattening of synthesis		 fransschreuder 3612d 18h /
4 fixed a typo in the interrupt table documentation fransschreuder 3624d 15h /
3 Created:
First commit of the full PCIe DMA Core
Including:
-Firmware
-Vivado .tcl scripts
-Questasim simulation scripts
-Documentation (Latex / Doxygen script)		 fransschreuder 3624d 15h /
2 Added firmware directory fransschreuder 3627d 13h /
1 The project and the structure was created root 3646d 08h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.