URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] - Rev 8

Rev	Log message	Author	Age	Path
8	Changed: * Added support for circular DMA (wrap around) * Fixed Read / Write interrupts	fransschreuder	3566d 03h	/
7	Changed: * Simplified address calculation to relax timing * Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing * Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk * Added support for the High tech Global HTG710 board	fransschreuder	3605d 22h	/
6	Changed: * fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable * Fixed missing signals in sensitivity list	fransschreuder	3611d 21h	/
5	Changed: * Added two registers to test interrupts vectors 2 and 3 * Added a register to read generic constants to show number of interrupts / number of descriptors * fixed consistency of generic default values among different design units * fixed route of pll_locked / register map record, to allow non-flattening of synthesis	fransschreuder	3613d 00h	/
4	fixed a typo in the interrupt table documentation	fransschreuder	3624d 21h	/
3	Created: First commit of the full PCIe DMA Core Including: -Firmware -Vivado .tcl scripts -Questasim simulation scripts -Documentation (Latex / Doxygen script)	fransschreuder	3624d 21h	/
2	Added firmware directory	fransschreuder	3627d 19h	/
1	The project and the structure was created	root	3646d 15h	/