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Rev Log message Author Age Path
13 - interim release w11a_V0.532 (untagged)
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
wfjm 4752d 19h /
12 - interim release w11a_V0.531 (untagged)
- many small changes to prepare upcoming support for Spartan-6 and
usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
wfjm 4821d 10h /
11 - final touch-up for V0.53 minor release wfjm 4969d 19h /
10 - add sources for C++/Tcl based backend, add directories
- tools/src/...
- tools/tcl/...
- tools/dox
- tools/make
- add rlink test system
- rtl/sys_gen/tst_rlink/nexys2/...
wfjm 4984d 20h /
9 - interim release w11a_V0.52 (untagged)
- migrate to rbus protocol verion 3
- reorganize rbus and rlink modules, many renames
wfjm 5074d 18h /
8 - interim release w11a_V0.51 (untagged)
- migrate to ibus protocol verion 2
- nexys2 systems now with DCM derived system clock supported
- sys_w11a_n2 now runs with 58 MHz clksys
wfjm 5110d 08h /
7 tag w11a_V0.5 wfjm 5237d 12h /
6 last touchup of README.txt wfjm 5237d 13h /
5 additional documentation wfjm 5238d 12h /
4 additional documentation wfjm 5244d 12h /
3 setup all svn:ignore props wfjm 5251d 13h /
2 initial source upload (no docs yet) wfjm 5251d 13h /
1 The project and the structure was created root 5254d 13h /

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