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Subversion Repositories wb2axip

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Rev Log message Author Age Path
18 Updated svn:ignore properties dgisselq 2097d 15h /
17 Updating svn:ignore properties dgisselq 2097d 15h /
16 Lots of updates (see below)

New files:
1. AXI-lite formal checker(s)
2. AXI-lite to WB bridge
3. WB to AXI-lite bridge
4. WB cross bar (for lack of a better place)
5. Demonstration/example AXI-lite core

Other files have been updated as necessary. Ex. the WB formal checker files.		 dgisselq 2101d 01h /
15 Quick update, making this module verilatable again dgisselq 2461d 04h /
14 Added a reset line upon user request dgisselq 2461d 04h /
13 Bug fix release--fixes the bugs Antti pointed out. dgisselq 2473d 18h /
12 Added Verilators obj_dir to the list of ignored files dgisselq 2571d 05h /
11 Updated the bench/formal properties

SVN will now ignore the build files associated with this directory: *.smt2,
*.yslog, *.vcd		 dgisselq 2571d 05h /
10 Added files to flush out the formal proof capability dgisselq 2571d 05h /
9 Added a formal directory dgisselq 2571d 05h /
8 The WB to AXI translator wrks and works well.

A proof of this will be added shortly.		 dgisselq 2571d 05h /
7 Simplified. dgisselq 2888d 05h /
6 IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet) dgisselq 3016d 01h /
5 Adjusted variable names to match the spec and the MIG. dgisselq 3020d 16h /
4 Adjusted the core quickly so it should work for 128-bit wide wishbone busses
as well as 32-bit wide busses.		 dgisselq 3020d 22h /
3 Fixed the Verilator compile-time bugs. Still haven't tested the core. dgisselq 3020d 22h /
2 Initial check in. Core not (yet) tested, verified, or validated. dgisselq 3020d 23h /
1 The project and the structure was created root 3020d 23h /

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