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Rev Log message Author Age Path
38 Included some Xilinx compiler related fixes from Howard Harte bporcella 6287d 21h /
37 Included some typo-type fixes from Howard Harte bporcella 6287d 21h /
36 added test for HH's IN bug bporcella 6292d 00h /
35 added fix for IN bug found by howard bporcella 6292d 01h /
34 revert to rev 1 as rev 2 seems unreadable binary file checkin problem ? bporcella 6293d 22h /
33 revert to rev 1 as rev 2 seems unreadable binary file checkin problem ? bporcella 6293d 23h /
32 fixed bugs and augmented instruction test.
ex de hl bug fixed thanks Howard Harte
ret condition (ret not taken bug) thanks - Stephen Warren
bporcella 6301d 22h /
31 some fixes found in synthesis bporcella 7517d 22h /
30 test executes cleanly bporcella 7525d 04h /
29 logic movd to z80_sram.v bporcella 7525d 04h /
28 logic movd to z80_bist_logic.v bporcella 7525d 04h /
27 Instruction test (with interrupts) runs!!! bporcella 7525d 04h /
26 inst test got to the worked macro bporcella 7531d 15h /
25 instruction test getting to final stages bporcella 7533d 20h /
24 testbed built and verification in progress bporcella 7539d 00h /
23 testbed built and verification in progress bporcella 7539d 03h /
22 testbed files bporcella 7539d 03h /
21 build script bporcella 7539d 03h /
20 check in test files and assembler manual bporcella 7539d 03h /
19 chckin for ease of use bporcella 7539d 03h /

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