URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] - Rev 8

Rev	Log message	Author	Age	Path
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	3043d 22h	/
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	3045d 08h	/
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	3046d 07h	/
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	3046d 14h	/
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	3047d 06h	/
3	Fixes some, not all, of the Verilator build/lint errors.	dgisselq	3047d 21h	/
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	3047d 23h	/
1	The project and the structure was created	root	3048d 03h	/