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Rev Log message Author Age Path
9 Updated the scope so that it compiles into block RAM within Xilinx's XST. dgisselq 3339d 10h /
8 Fixed a minor bug that Vivado found, but one that would've prevented the
compressed scope from working.		 dgisselq 3424d 10h /
7 Adjusted the version number of the Specification. (Oops--I had just checked
the new version in without adjusting the version number ...)		 dgisselq 3425d 13h /
6 This update reflects very minor to the scope documentation/spec to make it
more readable.

Also included in this release is an update to the compressed scope. This
update changes the compressed scope from working with absolute addresses to
difference addresses. This latter scope and mode has not been tested (yet),
so I can't vouch for how well it will (or won't) work. It is provided, as
the documentation states, for discussion purposes.		 dgisselq 3425d 13h /
5 Further changes to the specification document, fixing the prior document's
failure to build, updating the formatting for ports, states, and pins, and
other minor fixes.		 dgisselq 3448d 05h /
4 Adjusted the spec further, filling in such further details as were missing.
This should be a better first draft than before.		 dgisselq 3448d 07h /
3 Added the compressed wishbone scope for discussion purposes. The design/spec
on this compressed scope is not complete, nor is it clear what would constitute
complete, but it is provided to provoke some discussion.		 dgisselq 3448d 11h /
2 First draft of the documentation, perhaps not complete. However, the scope
is complete and has passed quite a bit of testing.		 dgisselq 3448d 12h /
1 The project and the structure was created root 3448d 13h /

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