OpenCores
URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] - Rev 15

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
15 Added a set of lite-UARTs that only handle 8N1 to the repository. dgisselq 2625d 01h /
14 This version works on hardware. dgisselq 2660d 03h /
13 Adjusted documentation of OPT_STANDALONE, and updated internal README files. dgisselq 2660d 23h /
12 Added hardware flow control information to the specification. dgisselq 2660d 23h /
11 Modified mkspeech to create both hex and include files, to tailor for the broken ISE program. dgisselq 2660d 23h /
10 Adjusted for the new hardware flow control capability. dgisselq 2661d 00h /
9 Added a hardware flow control capability. dgisselq 2661d 00h /
8 Updated the documents to reference the new testbenches. dgisselq 2692d 03h /
7 Moved the definition of state to before its first usage. dgisselq 2692d 03h /
6 Lots of changes--see the git log for the full details. dgisselq 2695d 05h /
5 Created independent peripheral, several toplevel tests, and updated documentation to match. dgisselq 2705d 15h /
4 "make clean" now works, with the added -rf to the rm commands. dgisselq 2832d 05h /
3 This fixes a bug in the UARTSIM module whereby the number of counts per baud
wasn't equal to the number given in the setup. The previous version worked
for count numbers greater than 25 (where I had tested it), but not for low
count numbers like 4. This version has now been tested, and is known to work
with baud counts as low as 4.		 dgisselq 2835d 06h /
2 A first version to be checked in. The rxuart.v and txuart.v files have been
well tested elsewhere, although the test setup here has not been as well tested.
Still, type 'make test' in the base directory and you will get an assurance
that the entire thing works--if you would like.		 dgisselq 2839d 00h /
1 The project and the structure was created root 2839d 12h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.