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Rev Log message Author Age Path
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5544d 03h /
11 Update with Single Step debuging test rehayes 5544d 03h /
10 Minor Cleanup rehayes 5549d 03h /
9 Update for new testbench usage rehayes 5550d 01h /
8 Clean up, Fix default ISR rehayes 5550d 01h /
7 Fix to take advantage of change to sconv program. rehayes 5556d 00h /
6 Update to create output file name from input file name by changing extension to .v rehayes 5556d 00h /
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5557d 03h /
4 Clean up rehayes 5565d 00h /
3 Clean up rehayes 5565d 00h /
2 Initial Checkin rehayes 5565d 01h /
1 The project was created and the structure was created root 5597d 05h /

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