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Rev Log message Author Age Path
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5309d 23h /
52 Minor changes to aide waveform debug rehayes 5309d 23h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5325d 19h /
50 incremental update to match status bit changes rehayes 5325d 19h /
49 First pass with instruction set details rehayes 5325d 19h /
48 Update for SBC ana ADC condition code changes rehayes 5325d 19h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5325d 20h /
46 Update to remove stack registers and add new register text. rehayes 5357d 18h /
45 Update to remove stack registers and add new register text. rehayes 5357d 18h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5359d 16h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5359d 17h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5359d 17h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5360d 19h /
40 Update for single program counter adder rehayes 5380d 22h /
39 delete rehayes 5388d 23h /
38 Nov 9 2009 update notes rehayes 5388d 23h /
37 RAM model breakout for testbench rehayes 5389d 00h /
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5389d 00h /
35 Add byte lane select input to all tasks rehayes 5389d 00h /
34 minor changes related to wishbone master interface rehayes 5389d 00h /

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