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Rev Log message Author Age Path
60 Add ability at insert wait states on RAM access rehayes 5239d 05h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5239d 05h /
58 WISHBONE Bus update. rehayes 5291d 05h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5291d 08h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5307d 08h /
55 Minor change to instruction set details. rehayes 5307d 08h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5307d 09h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5307d 09h /
52 Minor changes to aide waveform debug rehayes 5307d 09h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5323d 05h /
50 incremental update to match status bit changes rehayes 5323d 05h /
49 First pass with instruction set details rehayes 5323d 05h /
48 Update for SBC ana ADC condition code changes rehayes 5323d 05h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5323d 06h /
46 Update to remove stack registers and add new register text. rehayes 5355d 04h /
45 Update to remove stack registers and add new register text. rehayes 5355d 04h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5357d 02h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5357d 03h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5357d 03h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5358d 05h /

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