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Rev Log message Author Age Path
60 Add ability at insert wait states on RAM access rehayes 5379d 19h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5379d 19h /
58 WISHBONE Bus update. rehayes 5431d 19h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5431d 22h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5447d 22h /
55 Minor change to instruction set details. rehayes 5447d 23h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5447d 23h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5447d 23h /
52 Minor changes to aide waveform debug rehayes 5447d 23h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5463d 19h /
50 incremental update to match status bit changes rehayes 5463d 19h /
49 First pass with instruction set details rehayes 5463d 19h /
48 Update for SBC ana ADC condition code changes rehayes 5463d 20h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5463d 20h /
46 Update to remove stack registers and add new register text. rehayes 5495d 18h /
45 Update to remove stack registers and add new register text. rehayes 5495d 18h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5497d 16h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5497d 17h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5497d 17h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5498d 19h /

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