OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 61

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5346d 10h /
60 Add ability at insert wait states on RAM access rehayes 5346d 11h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5346d 11h /
58 WISHBONE Bus update. rehayes 5398d 10h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5398d 13h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5414d 14h /
55 Minor change to instruction set details. rehayes 5414d 14h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5414d 14h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5414d 14h /
52 Minor changes to aide waveform debug rehayes 5414d 14h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5430d 10h /
50 incremental update to match status bit changes rehayes 5430d 11h /
49 First pass with instruction set details rehayes 5430d 11h /
48 Update for SBC ana ADC condition code changes rehayes 5430d 11h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5430d 11h /
46 Update to remove stack registers and add new register text. rehayes 5462d 09h /
45 Update to remove stack registers and add new register text. rehayes 5462d 10h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5464d 08h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5464d 08h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5464d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.