URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 65

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Rev	Log message	Author	Age	Path
65	Parameterize delays based on number of RAM wait states.	rehayes	5311d 08h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5311d 08h	/
63	Remove historical output ports that are no longer used.	rehayes	5321d 07h	/
62	Cleanup implicit wire declarations.	rehayes	5321d 07h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5328d 07h	/
60	Add ability at insert wait states on RAM access	rehayes	5328d 07h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5328d 07h	/
58	WISHBONE Bus update.	rehayes	5380d 07h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5380d 10h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5396d 11h	/
55	Minor change to instruction set details.	rehayes	5396d 11h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5396d 11h	/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5396d 11h	/
52	Minor changes to aide waveform debug	rehayes	5396d 11h	/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5412d 07h	/
50	incremental update to match status bit changes	rehayes	5412d 07h	/
49	First pass with instruction set details	rehayes	5412d 08h	/
48	Update for SBC ana ADC condition code changes	rehayes	5412d 08h	/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5412d 08h	/
46	Update to remove stack registers and add new register text.	rehayes	5444d 06h	/

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Subversion Repositories xgate

[/] - Rev 65

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