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Rev Log message Author Age Path
70 Updated with interrupt bypass controll registers. rehayes 5167d 10h /
69 New test to verify irq interrupt priority encoder. rehayes 5167d 10h /
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5167d 11h /
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5167d 11h /
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5187d 06h /
65 Parameterize delays based on number of RAM wait states. rehayes 5187d 07h /
64 Fixed more bugs related to wait states and debug mode. rehayes 5187d 07h /
63 Remove historical output ports that are no longer used. rehayes 5197d 06h /
62 Cleanup implicit wire declarations. rehayes 5197d 06h /
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5204d 06h /
60 Add ability at insert wait states on RAM access rehayes 5204d 06h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5204d 06h /
58 WISHBONE Bus update. rehayes 5256d 05h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5256d 09h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5272d 09h /
55 Minor change to instruction set details. rehayes 5272d 09h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5272d 09h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5272d 09h /
52 Minor changes to aide waveform debug rehayes 5272d 10h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5288d 06h /

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