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Rev	Log message	Author	Age	Path
78	Added IRQ bypass registers and Test bench appendix	rehayes	5280d 06h	/
77	Documentation update	rehayes	5280d 06h	/
76	Updated xgate_risc.v for xlink synthesis warnings.	rehayes	5303d 07h	/
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5303d 08h	/
74	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5308d 09h	/
73	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5308d 09h	/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5308d 09h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5309d 11h	/
70	Updated with interrupt bypass controll registers.	rehayes	5309d 11h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5309d 12h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5309d 12h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5309d 12h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5329d 08h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5329d 08h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5329d 08h	/
63	Remove historical output ports that are no longer used.	rehayes	5339d 07h	/
62	Cleanup implicit wire declarations.	rehayes	5339d 07h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5346d 07h	/
60	Add ability at insert wait states on RAM access	rehayes	5346d 07h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5346d 07h	/

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Subversion Repositories xgate

[/] - Rev 78

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