URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] - Rev 22

Rev	Log message	Author	Age	Path
22	Added prototype system verilog testbench	antanguay	4387d 09h	/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4387d 10h	/
20	Updates for Xilinx synthesis	antanguay	4677d 04h	/
19	Updates for 32/64 bit systems	antanguay	4852d 05h	/
18	Updates for linux 32-bit	antanguay	4853d 02h	/
17	Fixed deprecated SystemC warnings	antanguay	4855d 09h	/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4855d 16h	/
15	Updated for Verilator 3.813	antanguay	4874d 16h	/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5463d 11h	/
13	Change interface to big endian, added serdes examples to testbench	antanguay	5463d 11h	/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5463d 11h	/
11	Fixed clock crossing	antanguay	5569d 09h	/
10	Added details to spec	antanguay	5667d 04h	/
9	Added old uploaded documents to new repository.	root	5741d 15h	/
8	Added old uploaded documents to new repository.	root	5741d 21h	/
7	New directory structure.	root	5741d 21h	/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	6018d 05h	/
5	Fixed compilation	antanguay	6024d 05h	/
4	Created	antanguay	6024d 07h	/
3	This commit was manufactured by cvs2svn to create tag 'initial'.		6024d 08h	/