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Rev Log message Author Age Path
22 Added prototype system verilog testbench antanguay 4571d 04h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4571d 04h /
20 Updates for Xilinx synthesis antanguay 4860d 23h /
19 Updates for 32/64 bit systems antanguay 5036d 00h /
18 Updates for linux 32-bit antanguay 5036d 21h /
17 Fixed deprecated SystemC warnings antanguay 5039d 04h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 5039d 11h /
15 Updated for Verilator 3.813 antanguay 5058d 11h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5647d 06h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5647d 06h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5647d 06h /
11 Fixed clock crossing antanguay 5753d 04h /
10 Added details to spec antanguay 5850d 23h /
9 Added old uploaded documents to new repository. root 5925d 10h /
8 Added old uploaded documents to new repository. root 5925d 16h /
7 New directory structure. root 5925d 16h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 6201d 23h /
5 Fixed compilation antanguay 6208d 00h /
4 Created antanguay 6208d 02h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 6208d 03h /

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