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Rev Log message Author Age Path
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4385d 12h /
24 Use FIFO's for statistics clock domain crossing antanguay 4385d 13h /
23 Adding basic packet stats antanguay 4385d 19h /
22 Added prototype system verilog testbench antanguay 4387d 16h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4387d 16h /
20 Updates for Xilinx synthesis antanguay 4677d 11h /
19 Updates for 32/64 bit systems antanguay 4852d 12h /
18 Updates for linux 32-bit antanguay 4853d 08h /
17 Fixed deprecated SystemC warnings antanguay 4855d 16h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4855d 23h /
15 Updated for Verilator 3.813 antanguay 4874d 23h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5463d 17h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5463d 18h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5463d 18h /
11 Fixed clock crossing antanguay 5569d 16h /
10 Added details to spec antanguay 5667d 11h /
9 Added old uploaded documents to new repository. root 5741d 22h /
8 Added old uploaded documents to new repository. root 5742d 03h /
7 New directory structure. root 5742d 03h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 6018d 11h /

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