URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

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Rev	Log message	Author	Age	Path
26	Added test data for 32k memory. Added GTKW configuration file.	lcdsgmtr	3484d 14h	/
25	Problem with memory: created conditional generate based upon data width instead of address width.	lcdsgmtr	3484d 14h	/
24	Starting tracing through the component hierarchy initialisation.	lcdsgmtr	3484d 14h	/
23	Currently moved test bench to 10 bit address. Created spreadsheet for filling memory with random data. When testing, memory is apparently not initialised.	lcdsgmtr	3484d 14h	/
22	Update on makefile, because some parts are in other files.	lcdsgmtr	3484d 14h	/
21	Since all BRAM is unified in one component, this testbench is not necessary anymore.	lcdsgmtr	3484d 14h	/
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3484d 14h	/
19	Makefile for building memory block testbench.	lcdsgmtr	3484d 14h	/
18	Ignore work files from GHDL.	lcdsgmtr	3484d 14h	/
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3484d 14h	/
16	Re-write of memory in function of initial array memory blocks.	lcdsgmtr	3484d 14h	/
15	Unification of all RAM parts into one interface.	lcdsgmtr	3484d 14h	/
14	Simple implementation project.	lcdsgmtr	3616d 13h	/
13	Updated smallest Xilinx configuration.	lcdsgmtr	3616d 13h	/
12	Update Xilinx configurations.	lcdsgmtr	3616d 13h	/
11	Successful run of the simulation. Correct results.	lcdsgmtr	3616d 15h	/
10	Correct build with GHDL.	lcdsgmtr	3616d 15h	/
9	This makes sure that this GHDL configuration analyses correctly.	lcdsgmtr	3616d 15h	/
8	Rebuilding the configuration to build the first system using GHDL.	lcdsgmtr	3617d 13h	/
7	Moved package for initialising memory also to src.	lcdsgmtr	3617d 13h	/

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Subversion Repositories xucpu

[/] - Rev 26

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