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32 Added necessary red tape for implementing all these components. lcdsgmtr 3272d 04h /
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 3272d 04h /
30 First implementation of cache memory. lcdsgmtr 3272d 04h /
29 All kinds of changes in different configurations. lcdsgmtr 3272d 04h /
28 Added project files for different systems. lcdsgmtr 3424d 06h /
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3424d 06h /
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3426d 04h /
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3426d 04h /
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3426d 04h /
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3426d 04h /
22 Update on makefile, because some parts are in other files. lcdsgmtr 3426d 04h /
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3426d 04h /
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3426d 04h /
19 Makefile for building memory block testbench. lcdsgmtr 3426d 04h /
18 Ignore work files from GHDL. lcdsgmtr 3426d 04h /
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3426d 04h /
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3426d 04h /
15 Unification of all RAM parts into one interface. lcdsgmtr 3426d 04h /
14 Simple implementation project. lcdsgmtr 3558d 03h /
13 Updated smallest Xilinx configuration. lcdsgmtr 3558d 03h /

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