| Rev |
Log message |
Author |
Age |
Path |
| 102 |
Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds. |
dgisselq |
3068d 03h |
/ |
| 101 |
Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare. |
dgisselq |
3068d 03h |
/ |
| 100 |
Includes updates so this can run at higher clocks speeds within an FPGA. |
dgisselq |
3068d 04h |
/ |
| 99 |
Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform. |
dgisselq |
3068d 04h |
/ |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
3068d 04h |
/ |
| 97 |
Latest working bit file, with all changes attached as of this date. |
dgisselq |
3091d 07h |
/ |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
3091d 07h |
/ |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
3091d 07h |
/ |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
3091d 07h |
/ |
| 93 |
Oops -- missed adjusting the copyright. |
dgisselq |
3091d 08h |
/ |
| 92 |
Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger. |
dgisselq |
3091d 08h |
/ |
| 91 |
Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned. |
dgisselq |
3091d 08h |
/ |
| 90 |
Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional. |
dgisselq |
3091d 08h |
/ |
| 89 |
Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done. |
dgisselq |
3091d 08h |
/ |
| 88 |
Adjusted copyright date. |
dgisselq |
3091d 08h |
/ |
| 87 |
Placed the interrupt into the carry chain for less logic area. |
dgisselq |
3091d 08h |
/ |
| 86 |
Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth. |
dgisselq |
3091d 08h |
/ |
| 85 |
First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.) |
dgisselq |
3095d 05h |
/ |
| 84 |
First part of switching to proper sdspi.v, and not just the link. |
dgisselq |
3095d 05h |
/ |
| 83 |
Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port. |
dgisselq |
3096d 08h |
/ |
