| Rev |
Log message |
Author |
Age |
Path |
| 103 |
Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.) |
dgisselq |
3065d 14h |
/ |
| 102 |
Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds. |
dgisselq |
3065d 14h |
/ |
| 101 |
Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare. |
dgisselq |
3065d 15h |
/ |
| 100 |
Includes updates so this can run at higher clocks speeds within an FPGA. |
dgisselq |
3065d 15h |
/ |
| 99 |
Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform. |
dgisselq |
3065d 15h |
/ |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
3065d 15h |
/ |
| 97 |
Latest working bit file, with all changes attached as of this date. |
dgisselq |
3088d 19h |
/ |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
3088d 19h |
/ |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
3088d 19h |
/ |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
3088d 19h |
/ |
| 93 |
Oops -- missed adjusting the copyright. |
dgisselq |
3088d 19h |
/ |
| 92 |
Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger. |
dgisselq |
3088d 19h |
/ |
| 91 |
Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned. |
dgisselq |
3088d 19h |
/ |
| 90 |
Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional. |
dgisselq |
3088d 19h |
/ |
| 89 |
Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done. |
dgisselq |
3088d 19h |
/ |
| 88 |
Adjusted copyright date. |
dgisselq |
3088d 19h |
/ |
| 87 |
Placed the interrupt into the carry chain for less logic area. |
dgisselq |
3088d 19h |
/ |
| 86 |
Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth. |
dgisselq |
3088d 19h |
/ |
| 85 |
First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.) |
dgisselq |
3092d 16h |
/ |
| 84 |
First part of switching to proper sdspi.v, and not just the link. |
dgisselq |
3092d 16h |
/ |
