| Rev |
Log message |
Author |
Age |
Path |
| 112 |
Provides a simulated UART capability to the busmaster_tb simulation. |
dgisselq |
3055d 08h |
/ |
| 111 |
Added some debug support programs to the repository. |
dgisselq |
3061d 02h |
/ |
| 110 |
Fixed a problem whereby block RAM would be declared as a bus error on the
stack, even if the data was valid. |
dgisselq |
3061d 06h |
/ |
| 109 |
This continues the updates to the wishbone-uart conversion. It fixes several
bugs within wbuexec, and pipelines the compression scheme. Further, the
read codeword was adjusted so that a read of 8 can be requested with six-bits,
rather than requiring 12. Likewise, the dependence upon the read of 8 on
incrementing the address pointer has been removed. All told, the design
builds for a 200MHz Artix-7, and it has been tested with the CMod-S6. (Writing
flash seems to be one of the most comprehensive tests ...) |
dgisselq |
3061d 11h |
/ |
| 108 |
Minor documentation updates. |
dgisselq |
3061d 21h |
/ |
| 107 |
Minor change. |
dgisselq |
3061d 21h |
/ |
| 106 |
Minor, inconsequential changes. |
dgisselq |
3061d 21h |
/ |
| 105 |
Mostly cosmetic changes. The Makefile now builds a couple more programs,
the documentation is better, etc. |
dgisselq |
3061d 21h |
/ |
| 104 |
Updates to the flash driver drawn from the S6SoC project. |
dgisselq |
3061d 21h |
/ |
| 103 |
Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.) |
dgisselq |
3061d 21h |
/ |
| 102 |
Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds. |
dgisselq |
3061d 21h |
/ |
| 101 |
Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare. |
dgisselq |
3061d 21h |
/ |
| 100 |
Includes updates so this can run at higher clocks speeds within an FPGA. |
dgisselq |
3061d 21h |
/ |
| 99 |
Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform. |
dgisselq |
3061d 21h |
/ |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
3061d 21h |
/ |
| 97 |
Latest working bit file, with all changes attached as of this date. |
dgisselq |
3085d 01h |
/ |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
3085d 01h |
/ |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
3085d 01h |
/ |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
3085d 01h |
/ |
| 93 |
Oops -- missed adjusting the copyright. |
dgisselq |
3085d 01h |
/ |
