| Rev |
Log message |
Author |
Age |
Path |
| 114 |
Added ZipBones to the list of dependencies, so this will (should) build
properly for the XULA9 as well as the XULA25. |
dgisselq |
3146d 17h |
/ |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
3146d 17h |
/ |
| 112 |
Provides a simulated UART capability to the busmaster_tb simulation. |
dgisselq |
3148d 22h |
/ |
| 111 |
Added some debug support programs to the repository. |
dgisselq |
3154d 16h |
/ |
| 110 |
Fixed a problem whereby block RAM would be declared as a bus error on the
stack, even if the data was valid. |
dgisselq |
3154d 21h |
/ |
| 109 |
This continues the updates to the wishbone-uart conversion. It fixes several
bugs within wbuexec, and pipelines the compression scheme. Further, the
read codeword was adjusted so that a read of 8 can be requested with six-bits,
rather than requiring 12. Likewise, the dependence upon the read of 8 on
incrementing the address pointer has been removed. All told, the design
builds for a 200MHz Artix-7, and it has been tested with the CMod-S6. (Writing
flash seems to be one of the most comprehensive tests ...) |
dgisselq |
3155d 01h |
/ |
| 108 |
Minor documentation updates. |
dgisselq |
3155d 11h |
/ |
| 107 |
Minor change. |
dgisselq |
3155d 11h |
/ |
| 106 |
Minor, inconsequential changes. |
dgisselq |
3155d 11h |
/ |
| 105 |
Mostly cosmetic changes. The Makefile now builds a couple more programs,
the documentation is better, etc. |
dgisselq |
3155d 11h |
/ |
| 104 |
Updates to the flash driver drawn from the S6SoC project. |
dgisselq |
3155d 11h |
/ |
| 103 |
Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.) |
dgisselq |
3155d 11h |
/ |
| 102 |
Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds. |
dgisselq |
3155d 12h |
/ |
| 101 |
Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare. |
dgisselq |
3155d 12h |
/ |
| 100 |
Includes updates so this can run at higher clocks speeds within an FPGA. |
dgisselq |
3155d 12h |
/ |
| 99 |
Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform. |
dgisselq |
3155d 12h |
/ |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
3155d 12h |
/ |
| 97 |
Latest working bit file, with all changes attached as of this date. |
dgisselq |
3178d 16h |
/ |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
3178d 16h |
/ |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
3178d 16h |
/ |
