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Rev Log message Author Age Path
26 Some bug fixes, and the long jump early branching integration. dgisselq 3265d 17h /
25 Fixing compile time warnings. dgisselq 3265d 17h /
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3271d 15h /
23 This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update.		 dgisselq 3274d 03h /
22 Added the mkdatev.pl file. (Oops!) dgisselq 3276d 19h /
21 Files, not links, to replace what were once broken links in this project. dgisselq 3327d 02h /
20 Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board.		 dgisselq 3327d 02h /
19 Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources.		 dgisselq 3327d 02h /
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3330d 17h /
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3330d 17h /
16 Updates to allow a test of the ICAP configuration interface. dgisselq 3330d 17h /
15 WORKING VERSION! ... or, at least the memory test works. dgisselq 3332d 13h /
14 Quick bug fix. dgisselq 3332d 13h /
13 This version is now working. (It probably would've worked before, but
everything is now working.)		 dgisselq 3332d 13h /
12 Modified to match the settings I'm now using within ISE. dgisselq 3332d 15h /
11 Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.)		 dgisselq 3332d 15h /
10 Changed the name of the memtest.s file. dgisselq 3332d 15h /
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3332d 15h /
8 Added an interface description to the comments at the top of the file. dgisselq 3335d 01h /
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3335d 01h /

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