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Rev Log message Author Age Path
65 Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers.		 dgisselq 3090d 18h /
64 First (verified) working version. dgisselq 3090d 18h /
63 Simplified logic. dgisselq 3090d 18h /
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 3090d 18h /
61 Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true.		 dgisselq 3090d 18h /
60 LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.		 dgisselq 3090d 19h /
59 Simplified logic. dgisselq 3090d 19h /
58 Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. dgisselq 3090d 19h /
57 Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX.		 dgisselq 3098d 18h /
56 Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer.		 dgisselq 3098d 18h /
55 Updated copyright notice. dgisselq 3098d 18h /
54 Updated copyright notice. dgisselq 3098d 18h /
53 Added a touch of error checking. dgisselq 3138d 19h /
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 3138d 19h /
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 3148d 17h /
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 3157d 20h /
49 Added some documentation to make the read and write calls easier to understand. dgisselq 3166d 20h /
48 Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ...		 dgisselq 3168d 22h /
47 Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.)		 dgisselq 3168d 22h /
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 3168d 22h /

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