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Rev Log message Author Age Path
77 Adds register names and values for the SD card interface. dgisselq 3094d 15h /
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.		 dgisselq 3094d 15h /
75 Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.)		 dgisselq 3094d 15h /
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 3094d 15h /
73 Simplified logic. dgisselq 3094d 15h /
72 Sets XULA25 as the default. dgisselq 3094d 15h /
71 Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more.		 dgisselq 3094d 15h /
70 Cosmetic (minor) update. dgisselq 3094d 15h /
69 Massive logic simplification. This is also the first (verified) working
version.		 dgisselq 3094d 15h /
68 Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation.		 dgisselq 3094d 15h /
67 Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid.		 dgisselq 3094d 15h /
66 Simplified logic (barely). dgisselq 3094d 15h /
65 Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers.		 dgisselq 3094d 15h /
64 First (verified) working version. dgisselq 3094d 15h /
63 Simplified logic. dgisselq 3094d 15h /
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 3094d 15h /
61 Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true.		 dgisselq 3094d 15h /
60 LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.		 dgisselq 3094d 16h /
59 Simplified logic. dgisselq 3094d 16h /
58 Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. dgisselq 3094d 16h /

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