OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 87

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
87 Placed the interrupt into the carry chain for less logic area. dgisselq 2918d 20h /
86 Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth.		 dgisselq 2918d 20h /
85 First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.)		 dgisselq 2922d 17h /
84 First part of switching to proper sdspi.v, and not just the link. dgisselq 2922d 17h /
83 Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port.		 dgisselq 2923d 21h /
82 dgisselq 2924d 16h /
81 Adds register values for the SD-Card registers. dgisselq 2924d 16h /
80 Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested).		 dgisselq 2924d 16h /
79 Adds 'bench' and 'sw' targets, and automatically builds them (now). dgisselq 2924d 16h /
78 Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result.		 dgisselq 2924d 16h /
77 Adds register names and values for the SD card interface. dgisselq 2924d 16h /
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.		 dgisselq 2924d 16h /
75 Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.)		 dgisselq 2924d 16h /
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 2924d 16h /
73 Simplified logic. dgisselq 2924d 16h /
72 Sets XULA25 as the default. dgisselq 2924d 16h /
71 Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more.		 dgisselq 2924d 16h /
70 Cosmetic (minor) update. dgisselq 2924d 17h /
69 Massive logic simplification. This is also the first (verified) working
version.		 dgisselq 2924d 17h /
68 Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation.		 dgisselq 2924d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.