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Rev Log message Author Age Path
10 Added a test system feddischson 3442d 23h /
9 Added first draft for a C driver feddischson 3442d 23h /
8 Added a file for processing one calculation (for debugging purpose) feddischson 3442d 23h /
7 Removed some bugs regarding pre-rotation and negative numbers in the wb wrapper feddischson 3442d 23h /
6 updated README.txt feddischson 3442d 23h /
5 added a wishbone bus wrapper feddischson 3442d 23h /
4 Updated C and RTL model as well as the documentation feddischson 3442d 23h /
3 initial commit feddischson 3442d 23h /
2 First stable version: RTL model is verified with C-model via RTL simulations. feddischson 3892d 10h /
1 The project and the structure was created root 3919d 13h /

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