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Rev Log message Author Age Path
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.		 dgisselq 3004d 00h /
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.		 dgisselq 3029d 12h /
198 Added a copyright notice. dgisselq 3030d 17h /
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 3030d 17h /
196 Updated internal documentation. dgisselq 3030d 17h /
195 Adds a new mode that can handle a delayed stall signal. dgisselq 3030d 17h /
194 Cleaned up some parameters, trying to create more consistency. dgisselq 3030d 17h /
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 3030d 17h /
192 Fixed a bug with constant alignment in the assembler. dgisselq 3030d 17h /
191 Updated toolchain, more information on the example debugger. dgisselq 3045d 20h /
190 Added the copyright statement back in. dgisselq 3047d 12h /
189 Final, as delivered, ORCONF slides. dgisselq 3047d 12h /
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.		 dgisselq 3079d 14h /
187 Updated to match changed register definitions within the core. dgisselq 3079d 15h /
186 Now allows profile dumping for ELF executables. dgisselq 3079d 15h /
185 Now includes the proper flags for building with ELF executable file support. dgisselq 3079d 15h /
184 Adjusted the illegal instruction option documentation. dgisselq 3079d 15h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 3079d 15h /
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.		 dgisselq 3079d 15h /
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.		 dgisselq 3079d 15h /

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