| Rev |
Log message |
Author |
Age |
Path |
| 46 |
A series of updates associated with getting Dhrystone to work. Includes
updates to getting multiple files to link/work together within the assembler,
as well as getting quoted quotations to work in the lexer, and better
include file support in the preprocessor. |
dgisselq |
3344d 18h |
/ |
| 45 |
Library routines for 32-bit multiply and divide, both signed and unsigned. |
dgisselq |
3344d 18h |
/ |
| 44 |
?? |
dgisselq |
3344d 18h |
/ |
| 43 |
Minor edits to the C++ testbench. |
dgisselq |
3344d 18h |
/ |
| 42 |
Oops -- forgot to add the stack. |
dgisselq |
3344d 18h |
/ |
| 41 |
Assembly file for the Dhrystone benchmark added. |
dgisselq |
3344d 18h |
/ |
| 40 |
Quick update, updates the assembly for the new version of the assembler. |
dgisselq |
3344d 18h |
/ |
| 39 |
Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked. |
dgisselq |
3347d 21h |
/ |
| 38 |
A couple of quick updates:
- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.
Documentation changes coming shortly. |
dgisselq |
3347d 23h |
/ |
| 37 |
Fixed some minor spelling errors. |
dgisselq |
3356d 14h |
/ |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3357d 02h |
/ |
| 35 |
I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache. |
dgisselq |
3373d 17h |
/ |
| 34 |
Bunches of changes, although very little changed with the core itself.
Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the
core), so that the debugger can change the program counter. The debugger
can now halt the CPU and then view, examine, and modify registers to include
the program counter, although live changes to the CC register have not been
tested.
There was also a bug in the stall handling of the wishbone bus delay line. This
has now been fixed.
Moving outwards to the system, some parameters have been added to zipsystem
to make it more configurable for whatever environment you might wish to place
it within. Other minor clean ups have taken place, mostly to the internal
documentation.
Lots of changes, though, to the assembler. The big one is the implementation
of #define macros, C style. Several buggy macros were in sys.i. These have
been fixed. The Makefile has been adjusted so that the build of test.S, which
depends upon sys.i, is now properly dependent upon sys.i for make purposes.
Further, not only will zpp, the assembler preprocessor, handle #define macros,
it will also recursive #defines. The assembler expression evaluator has also
been updated to properly handle both operator precedence, as well as modulo
arithmetic.
The master system test file, test.S, found in the sw/zasm directory has been
updated to reflect these new capabilities. (I really need to move it to the
bench/asm directory, so you may expect that change sometime later.) |
dgisselq |
3382d 21h |
/ |
| 33 |
Finally finished a first draft of the full specification! |
dgisselq |
3385d 20h |
/ |
| 32 |
Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.
The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create. |
dgisselq |
3386d 03h |
/ |
| 31 |
README now comments on the relationship between the debugger and the
test bench. (They came from the same code at one time ...) |
dgisselq |
3386d 05h |
/ |
| 30 |
Here's a 20% increase in performance: We've gone from 0.44 clocks per
instruction up to 0.53 clocks per instruction on the test.S testset. The
cost? Oh, only about 300 slices.
Not bad.
The specification document will also soon be updated with a list of
conditions that create stalls, as eliminating stalls was how I managed to get
the performance up like I did. |
dgisselq |
3386d 05h |
/ |
| 29 |
Not sure what this file was, but it isn't a part of the project anymore. |
dgisselq |
3386d 13h |
/ |
| 28 |
I got tired of running the make files across multiple directories, so I
built this makefile to coordinate building across each directory. |
dgisselq |
3386d 14h |
/ |
| 27 |
The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.
A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)
The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively. |
dgisselq |
3386d 14h |
/ |
